Dr. M. Surya Prakash

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Revision as of 15:43, 29 January 2024 by Vysakh Premkumar (talk | contribs) (Created page with "==Assistant Professor Grade II== Office Address: ECED-2 : 208, Department of Electronics and Communication Engineering National Institute of Technology Calicut, Kerala, India Contact no: 04952286734 Email ID: suryaprakash@nitc.ac.in ==Educational Qualifications== B.Tech, JNTU Kakinada, 2010 Ph.D, IIT Guwahati, 2016. ==Publications== ===Journals=== M. Prakash and R. Shaik, "Low-area and high-throughput architecture for an adaptive filter using di...")
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Assistant Professor Grade II

Office Address:

ECED-2 : 208, Department of Electronics and Communication Engineering National Institute of Technology Calicut, Kerala, India

Contact no:

04952286734

Email ID: suryaprakash@nitc.ac.in


Educational Qualifications

   B.Tech, JNTU Kakinada, 2010

   Ph.D, IIT Guwahati, 2016.

Publications

Journals

   M. Prakash and R. Shaik, "Low-area and high-throughput architecture for an adaptive filter using distributed arithmetic," IEEE Trans. Circ. Syst. II, Exp. Briefs., vol. 60, no. 11, pp. 781–785, Nov 2013.
   M. Prakash, R. Shaik and K. Sagar, "An Efficient Distributed Arithmetic based realization of the Decision Feedback Equalizer," Circ. Sys. and Sig. Process., Springer, vol. 35, issue. 2, pp. 603-618, Feb 2016.
   M. S. Prakash, R. Shaik, "DA based approach for the implementation of block adaptive decision feedback equalizer," IET Sig. Process., vol. 10(6), pp. 676-684, Aug 2016.
   Mohd Tasleem Khan, Rafi Ahamed Shaik, Surya Prakash M, "Improved convergent distributed arithmetic based low complexity pipelined least-mean-square filter," IET Circ., Dev., Sys., Apr 2018.
   M. Surya Prakash, Rafi Ahamed Shaik, "A Distributed Arithmetic Based Realization of Least Mean Square Adaptive Decision Feedback Equalizer Using Offset Binary Coding Scheme", Elsevier Signal Processing, 2021.
   P. Kopperundevi, M. Surya Prakash, Rafi Ahamed Shaik, "A High Throughput Hardware Architecture for Deblocking Filter in HEVC", Sig. Process.: Image Comm., vol.100, 2022.
   P. Kopperundevi, M. Surya Prakash, "Methods to Develop High Throughput Hardware Architectures for HEVC Deblocking Filter using Mixed Pipelined-Block Processing Techniques" Microelec. Journ., pp. 105413, vol. 123, 2022.

Conferences

   M. Surya Prakash and R. Shaik, "High performance architecture for LMS based adaptive filter using distributed arithmetic," in Int. Conf. Inform. and Comput. Applicat. (ICICA), vol. 24, pp. 18-22, Mar. 2012.
   M. Prakash and R. Shaik, "Low complexity hardware architectural design for adaptive decision feedback equalizer using distributed arithmetic," in IEEE Int. Conf. Comput. Syst. and Ind. Informatics (ICCSII), pp. 1-5, Dec. 2012.
   M. Surya Prakash and R. Shaik, "A Distributed Arithmetic based Approach for the Implementation of the Sign-LMS Adaptive Filter," in IEEE Int. Conf. on Sig. Process. and Commun. Eng. Syst. (SPACES), pp. 326-330, Jan. 2015.
   P. Kopperundevi, M. Surya Prakash, "A Hardware Architecture for Sample Adaptive Offset Filter in HEVC", accepted for publication in IEEE DISCOVER-2021.
   P. Kopperundevi and M. Surya Prakash, "Residue adder design for the modulo set {2n-1, 2n,2n+1-1} and its application in  DCT architecture for  HEVC," accepted for publication in proceedings of VLSI SATA-2022.
   P. Kopperundevi and M. Surya Prakash, "Multiplier Design for the Modulo Set {2n-1, 2n,2n+1-1} and its Application in DCT for HEVC," accepted for publication in proceedings of VSPICE-2022.
   Vidyamol K. and M. Surya Prakash, "An Improved Dark Channel Prior For Fast Dehazing of Outdoor Images," accepted for publication in proceedings of ICCCNT-2022.

Books (Refereed)

   Kopperundevi, P., and Surya Prakash, M., (2021) “An Efficient Hardware Architecture For Deblocking Filter in HEVC”, in chapter in Innovations in Springer Electrical and Electronic Engineering, vol. 661, Jan-2021.

Courses Handled

Semester Course Year of Study and Branch
Monsoon-2018 ZZ1003D Basic Electrical Sciences B. Tech Ist year (CSE, CE)
EC3091 Electronic Circuits-II Laboratory B. Tech IIIrd year (ECE)
Winter-2018 EC2091D Electronic Circuits-I B. Tech IInd year (ECE)
EC2093D Electronic Circuits-I laboratory B. Tech IInd year (ECE)
Monsoon-2019 ZZ1003D Basic Electrical Sciences B. Tech Ist year (ME, PE)
EC6402D Digital Signal Processing Algorithms M. Tech Ist year (ECE) (SP)
EC2091D Devices and Networks Laboratory B. Tech IInd year (ECE)
Winter-2019 ZZ1003D Basic Electrical Sciences B. Tech Ist year (ECE, EEE)
EC2091D Electronic Circuits-I B. Tech IInd year (ECE)
EC2093D Electronic Circuits-I Laboratory
Monsoon-2020 EC6402D Digital Signal Processing Algorithms M. Tech Ist year (ECE) (SP)
EC3013D Digital Signal Processing B. Tech IIIrd year (ECE)
Winter-2020


EC2021D Electronic Circuits-I B. Tech IInd year (ECE)
EC2093D Electronic Circuits-I Laboratory
EC3093D Digital Signal Processing Laboratory B. Tech IIIrd year (ECE)


Monsoon-2021


EC2011D Electric Circuits and Network Theory B. Tech IInd year (ECE)
EC2093D Devices and Networks Laboratory B. Tech IInd year (ECE)
Winter-2021 EC2024D Communication Theory and Systems-I B. Tech IInd year (ECE)
ZZ1003D Basic Electrical Sciences B. Tech Ist year (CSED, CED)
EC3093D Digital Signal Processing Laboratory B. Tech IIIrd year (ECED)

Extra-Academic Responsibilities Held

Year Title of the Program
2018-19
  1. Faculty Coordinator, ECE-Association (jointly with Dr. Dhanaraj K. J.).
  2. Member of the Exam Vigilance Committee of ECED (jointly with Shri. Suresh, Dr. Venu Anand and Dr. V. Sakthivel and Dr. Venu Anand).
  3. Member of the B. Tech Project Evaluation Committee for Embedded & VLSI specializations (jointly with Dr. Deepthi P. P. and Shri. Bhuvan B.).
  4. Member of the Volunteer Services Committee for 15th Convocation of NIT-Calicut.
  5. Member of M. Tech project Evaluation Team for Internship students.
  6. Member of Stock Verification Team for Annual Stock Verification 2018-19.
  7. Committee Member for Annual Sports Meet-2019 held at NIT-Calicut.
2019-20
  1. Time-table In-Charge for ECED (jointly with Dr. Bindiya T. S.).
  2. Member of the Exam Vigilance Committee of ECED (jointly with Dr. Ali C. K., Dr. Venu Anand and Dr. Sudeep P. V.).
  3. Member of the B. Tech Project Evaluation Committee for Embedded & VLSI specializations (along with Shri. Raghu C. V. and Shri. Bhuvan B.).
  4. Faculty Advisor for the 2019-23 batch of ECE students (jointly with Dr. Praveen Sankaran, Dr. Suja K. J. and Dr. Gopi Krishna S.).
  5. Member of the Announcements Committee for Annual Sports Day.
  6. Mentor Faculty from ECED for students internship under TEQIP Twinning program (jointly with Dr. Venu Anand).
  7. Application Scrutinization Committee member for Ad-hoc Faculty Interviews held during Monsoon-2019.
2020-21
  1. Time-table In-Charge for ECED (jointly with Dr. Bindiya T. S.).
  2. Faculty Incharge for Electronic Circuits Lab of ECED.
  3. Faculty Advisor for the 2019-23 batch of ECE students (jointly with Dr. Praveen Sankaran, Dr. Suja K. J. and Dr. Gopi Krishna S.).
  4. Committee Member for Disposal/Write-Off of unserviceable items.
  5. Committee Member for preparation of Self-Assessment Report (SAR) for MTech Telecommunications specialization.
  6. Member of the General Arrangements Committee for National Board of Accreditation Work for Telecommunications Specialization.

Conferences/Seminars/Webinars/Workshops/Training Sessions Attended

S. No. Title of the Program Venue Duration
1. TEQIP sponsored FDP on “ARM based Embedded System Development” ECED, NIT-Calicut. 7 days (17/06/2018 - 23/06/2018).
2. Workshop on Outcome Based Education & Institutional Academic Quality Assurance ECED, NIT-Calicut 1 day (13/12/2018)
3. TEQIP sponsored FDP on “Advanced Pedagogy Training Programme” Teaching Learning Centre, IIT Madras. 3 days (21/03/2019 - 23/03/2019).
4. Expert Talk on Signal Processing in FDP on “Research Trends in Multimedia and Multirate Signal Processing” (RTMMSP’19) ECED, NIT-Calicut, (By Prof. Sivaji Chakravorti) 6 days (24/06/2019 - 29/06/2019)
5. TEQIP sponsored Productivity Enhancement Program NIT-Calicut 4 days (16/07/2019 - 19/07/2019).
6. Expert Talk on “Control Path Design for Digital SOCs - using Embedded Processors” ECED, NIT-Calicut, (By Mathews John) 08/08/2019
7. TEQIP sponsored course on Digital Transformation in Teaching and Learning Process IIT Bombay (Online) 2 weeks (06/04/2020 - 22/04/2020).
8. Training for Xilinx Artix-7 AC701 Evaluation Kit Usage NIT-Calicut (Online) 22nd June, 2020
9. Two Hour Professional Workshop on “Prior-Art Searching with Google Patents” Turnip Innovations, Mumbai (Online) 05/09/2020
10. 30-Hour Live Online Instructor-led Training FDP on "Applied Machine Learning, AI & Its Applications Using Python" Eduxlabs in association with E-Cell, IIT Hyderabad 1st June, 2021 to 13th June, 2021
S. No. Title of the Program Venue Duration
1. Self Sponsored Five-Day Online Short Term Training Program (STTP) on “VLSI Architectures for Digital Signal Processing Systems” NIT-Calicut (Online, jointly with Dr. Ashutosh Mishra) 5 days (14th June, 2021 - 18th June, 2021)
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